Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
There is a constant need to shrink the size of the memory cell arrays in order to maximize the number of memory cells on a single wafer, while not sacrificing performance (i.e., program, erase and read efficiencies and reliabilities). It is well known that forming memory cells in pairs, with each pair sharing a single source region, and with adjacent pairs of cells sharing a common drain region, reduces the size of the memory cell array. It is also known to form trenches into the substrate, and locate one or more memory cell elements in the trench to increase the number of memory cells that fit into a given unit surface area (see for example U.S. Pat. Nos. 5,780,341 and 6,891,220). However, such memory cells use the control gate to both control the channel region (in a low voltage operation) and to erase the floating gate (in a high voltage operation). This means the control gate is both a low voltage and high voltage element, making it difficult to surround it with sufficient insulation for high voltage operation while not being too electrically isolated for low voltage operation. Moreover, the proximity of the control gate to the floating needed for an erase operation can result in unwanted levels of capacitive coupling between the control gate and the floating gate.
U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes, discloses a flash memory cell design that further includes an erase gate and a select gate (and a method of making them same in a self aligned manner). In this design, the channel region running along the surface of the substrate is controlled in part by a select gate and in part by the floating gate. The control gate is used to capacitively couple to the floating gate for programming, and the erase gate is used to remove the electrons from the floating gate. However, as the dimensions of the memory cell get smaller and smaller, it becomes more difficult to efficiently program the memory cell. Specifically, the portion of the channel region under the select gate used to generate hot electrons becomes too short for efficient hot electron injection programming.
Thus it is an object of the present invention to create a memory cell configuration and method of manufacture where the memory cell elements are self aligned to each other, and where smaller geometries can be achieved without sacrificing (and in fact improving) programming efficiency.